- Configurable to your specifications
- Rail-to-rail input voltage range
- High accuracy
- Low threshold offset voltage
- Programmable threshold voltage
- Programmable hysteresis
- Dynamic and static (latched) outputs
- Low propagation delay
- Low power consumption
The agileCMP GP programmable-threshold comparator features a user-selectable (enable/disable) hysteresis as well as programmable threshold with 10mV step size, a latched output as well as an active (unlatched) output.
With a focus on long battery life, the agileCMP GP can be used to monitor external analog signals and enable wake-up events - an essential in many modern SoCs.
The agileCMP GP programmable-threshold comparator is ideally suited for interrupt generation in applications such as in IoT, Security, Automotive, AI and general SoCs and ASICs.
Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. The agileCMP GP programmable-threshold comparator is available on CMOS and FD-SOI processes from 0.18um down to 22nm.
Our engineers have extensive experience in taking complex SoCs from design to mass production. We believe that success is not just measured by delivery of CDL and GDSII, rather it extends to mass production and beyond. This is reflected in the industry-leading quality of our deliverables. Our IP comes with a complete set of deliverables for ease of integration allowing our customers to produce their SoCs reliably, quickly and effortlessly.
- Design Report
- Integration model
- Functional model
- Timing model (.LIB)
- Layout Floorplanning (LEF)
- Netlist (CDL)
- Layout (GDSII)
- Physical Verification Report
- Tapeout Checklist
- Integration Guide
- Test Guide