agileADC – 8/10-bit SAR Analog-to-Digital Converter
The agileADC analog-to-digital converter is a traditional Charge-Redistribution SAR ADC that is referenced to VDD, VSS. The architecture can achieve up to 10-bit resolution at sample rates up to 20 MSps. It includes an eight-channel input multiplexor. Some inputs will be buffered inside the ADC, whereas others will bypass the buffer and be connected directly to the ADC to provide full rail-to-rail capability.
Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. We support all the major foundries including TSMC, GlobalFoundries, Samsung Foundry and SMIC as well as other IC foundries and Manufacturers. Please contact Agile Analog for further information.
Block Diagram:
Key Features:
- Resolution: 8bits/10bits
- Sampling Rate (Fs): 1 Msps to 20Msps
- Input Signal Bandwidth: Fs/2
- SINAD1: Typ 54dB
- SFDR1: Typ -60dBc
- CMRR2: min 65dB
- PSSR1: Typ 30dB
- Monotonic and no missing codes
- Customisable design for simple SoC integration
- Integrated Calibration Mode
- Silicon Area – Please contact Agile Analog
Benefits:
- DFT/DFM
- AMBA-APB Interface to simply test and operation
- Incorporated Trim and Calibration to facilitate process and/or manufacturing offsets to be adjusted
- Built-in test mode
Configurable Inputs:
- Upto 8 input channels
- Buffer or unbuffered
- Differential or Single-ended
- Rail-to-Rail input
System Macro:
- Combine with agileTsense and agileCMP to create a self-contained Temperature Sensor sub-system
- Threshold alarms and absolute value
- Configured to your exact specification
- Deliverables include Verilog-a, GDSII, Liberty, PVT/Monte Carlo analysis
