Analog IP the way you want it.
Using our configurable, multi-process analog IP platform methodology you can:
Work with any foundry on any node.
Optimise your analog designs, simplify your SoCs.
Reduce the cost of custom development.
Regain control of your analog IP design flow.
Reduce the complexity of analog IP integration.
Bring analog on chip as you need it.
Agile Analog offers a new approach, one that is free of the compromises, trade-offs and defects associated with standard, off-the-shelf analog IP. Offering highly configurable products for data conversion, security, power management and sensing, Agile Analog can generate new, optimised and fab-ready IP for each customer’s design.
Conventional off-the-shelf analog IP products typically snarl up the IC development process because of the re-work required to make them fit the application. With Agile Analog you will get analog IP exactly the way you want it.
Unlike standard off-the-shelf IP products, every Agile Analog IP is made fresh for each customer, with the features and specifications the application needs.
Agile Analog embeds foundries’ CMOS, FDSOI and FinFET design rules in the systems it uses to configure its IP products. So you can be sure that the IP which Agile Analog supplies to you is optimised for your foundry’s process and node.
EVENTS
MAY 31, 2022
Agile Analog announces Barry Paterson as its new CEO. With a career covering Cadence, Dialog, Intel, Maxim and Wolfson, Barry has been at the forefront of mixed signal semiconductor design and development for 30 years.
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APRIL 27, 2022
Agile Analog will establish an engineering team in Edinburgh, increasing the company’s design capabilities and allowing the business to reach more customers. Headquartered in Cambridge, Agile Analog’s technologies enable the rapid generation of high-quality analog IP.
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JANUARY 26, 2022
Establishment of a regional sales team follows a surge in demand for analog IP building blocks at advanced process nodes.
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MAY 23, 2022
Agile Analog™ was interviewed by Gabriéle to talk about how Agile Analog makes analog design automated possible.
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SEPTEMBER 7, 2021
Was amazing to see a number of glitch-led security attacks being presented, and a significant increase in the number of physical attack vectors. We really enjoyed these highlights in particular: Alex Matrosov and Adam Zabrocki showing the use of clock glitching to attack RISC-V CPUs, and a great response from RISC-V Foundation to set up a security response team.
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JUNE 1, 2021
Silicon Catalyst, the world’s only incubator focused exclusively on accelerating solutions in silicon, announced today, bringing Silicon Catalyst’s platform locally to the UK and European start- up community.
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Standard analog IP products from conventional IP suppliers are ready-made. That should be good, because – in theory – they are ready to be dropped into your IC design.
Except that’s not how it works in practice. Because off-the-shelf IP is ready-made, it’s never quite right for any application. That means the chip designer has to build in work-arounds to compensate for the features of the IP that do not fit their application.
The IP supplier might offer to modify its standard IP product, but modification often introduces bugs and defects which slow the customer’s path to tape-out. The solution is Agile Analog: you specify the IP you want, to include all the features you need and taking account of all your design constraints.
Using its unique Composa™ methodology, Agile Analog then generates the IP you have specified: fully tested, fully documented, bug-free and fab-ready.
Standard analog IP products from conventional IP suppliers are ready-made. That should be good, because – in theory – they are ready to be dropped into your IC design.
Except that’s not how it works in practice. Because off-the-shelf IP is ready-made, it’s never quite right for any application. That means the chip designer has to build in work-arounds to compensate for the features of the IP that do not fit their application.
The IP supplier might offer to modify its standard IP product, but modification often introduces bugs and defects which slow the customer’s path to tape-out. The solution is Agile Analog: you specify the IP you want, to include all the features you need and taking account of all your design constraints.
Using its unique Composa™ methodology, Agile Analog then generates the IP you have specified: fully tested, fully documented, bug-free and fab-ready.
Agile Analog IP is not a standard product with a pre-determined set of features and specifications. Using proprietary Composa™ methodology Agile Analog generates original IP for every new application.
That then enables us to optimise the IP to meet the unique requirements of your application. It’s what analog chip designers have been crying out for: we give you the choice over what to optimise for: accuracy, power consumption, die area, sensitivity, speed, or any other parameter – it’s up to you.
As analog engineers, we know that every analog circuit is different, with its own unique set of constraints and sensitivities. Now with Agile Analog, you can buy IP which reflects the unique characteristics of your design.
Agile Analog IP is not a standard product with a pre-determined set of features and specifications. Using proprietary Composa™ Methodology, Agile Analog generates original IP for every new application.
That then enables us to optimise the IP to meet the unique requirements of your application. It’s what analog chip designers have been crying out for: we give you the choice over what to optimise for: accuracy, power consumption, die area, sensitivity, speed, or any other parameter – it’s up to you.
As analog engineers, we know that every analog circuit is different, with its own unique set of constraints and sensitivities. Now with Agile Analog, you can buy IP which reflects the unique characteristics of your design.
This is one way in which Agile Analog IP is different from conventional, off-the-shelf analog IP. Standard IP products are typically targeted at a single foundry or process. To deploy that IP to a different process, it must be ‘ported’ – a hazardous exercise which tends to produce inferior performance and unexpected defects. So the time which the chip design team hoped to save by buying standard IP is lost in fixing the problems created by the porting process.
Agile Analog IP is different: because the IP is generated fresh via the unique Composa™ methodology, it is always optimised for the foundry, process and node in which it will be fabricated.
And the chip designer has total flexibility. Do you want to change node, process or even foundry mid-design? No problem. With Composa™ methodology, the same functional specifications and design optimisations can be applied, but with a new set of foundry design rules. And in less than four weeks from new specification to verified IP.
This is one way in which Agile Analog IP is different from conventional, off-the-shelf analog IP. Standard IP products are typically targeted at a single foundry or process. To deploy that IP to a different process, it must be ‘ported’ – a hazardous exercise which tends to produce inferior performance and unexpected defects. So the time which the chip design team hoped to save by buying standard IP is lost in fixing the problems created by the porting process.
Agile Analog IP is different: because the IP is generated fresh via the unique Composa™ methodology, it is always optimised for the foundry, process and node in which it will be fabricated.
And the chip designer has total flexibility. Do you want to change node, process or even foundry mid-design? No problem. With Composa™ methodology, the same functional specifications and design optimisations can be applied, but with a new set of foundry design rules. And in less than four weeks from new specification to verified IP.
When an ASIC or SoC designer evaluates standard, off-the-shelf analog IP, they are trying to discover which ready-made product best fits the specifications of their application.
With Agile Analog, you start from a completely different place: we ask you to consider how you can optimise your design given the constraints of your foundry and process.
Within the limits of what’s physically possible in silicon, the Agile Analog Composa™ platform can produce the exact IP that the designer wants for their application, and that includes integrating the optimal range of functions to minimise external component count, board footprint and system cost.
With the Composa™ methodology, Agile Analog generates IP for a wide range of functions including signal conditioning, data conversion, security, power management, timing and sensing.
Talk to Agile Analog and discover the scope for integrating multiple functions in one or more of these domains into your next chip design. contact
When an ASIC or SoC designer evaluates standard, off-the-shelf analog IP, they are trying to discover which ready-made product best fits the specifications of their application.
With Agile Analog, you start from a completely different place: we ask you to consider how you can optimise your design given the constraints of your foundry and process.
Within the limits of what’s physically possible in silicon, the Agile Analog Composa™ platform can produce the exact IP that the designer wants for their application, and that includes integrating the optimal range of functions to minimise external component count, board footprint and system cost.
With the Composa™ methodology, Agile Analog generates IP for a wide range of functions including signal conditioning, data conversion, security, power management, timing and sensing.
Talk to Agile Analog and discover the scope for integrating multiple functions in one or more of these domains into your next chip design.