Conventional off-the-shelf analog IP products typically snarl up the IC development process because of the re-work required to make them fit the application. Not Agile Analog IP: it’s the stuff analog engineers’ dreams are made of.

Standard analog IP products from conventional IP suppliers are ready-made. That should be good, because – in theory – they are ready to be dropped into your IC design. 

Except that’s not how it works in practice. Because off-the-shelf IP is ready-made, it’s never quite right for any application. That means the chip designer has to build in work-arounds to compensate for the features of the IP that do not fit their application. 

The IP supplier might offer to modify its standard IP product, but modification often introduces bugs and defects which slow the customer’s path to tape-out. The solution is Agile Analog: you specify the IP you want, to include all the features you need and taking account of all your design constraints. 

Using its unique COMPOSA methodology, Agile Analog then generates the IP you have specified: fully tested, fully documented, bug-free and fab-ready. 

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Unlike standard off-the-shelf IP products, every Agile Analog IP is made fresh for each customer, with the features and specifications the application needs.

Agile Analog IP is not a standard product with a pre-determined set of features and specifications. Using proprietary COMPOSA methodology, Agile Analog generates original IP for every new application.

That then enables us to optimise the IP to meet the unique requirements of your application. It’s what analog chip designers have been crying out for: we give you the choice over what to optimise for: accuracy, power consumption, die area, sensitivity, speed, or any other parameter – it’s up to you. 

As analog engineers, we know that every analog circuit is different, with its own unique set of constraints and sensitivities. 

Now with Agile Analog, you can buy IP which reflects the unique characteristics of your design. 

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The COMPOSA™ technology which generates Agile Analog IP embeds the CMOS design rules set by every important foundry. So you can be sure that the IP which Agile Analog supplies to you is optimized for your foundry, process and node.

This is one way in which Agile Analog IP is different from conventional, off-the-shelf analog IP. Standard IP products are typically targeted at a single foundry or process. To deploy that IP to a different process, it must be ‘ported’ – a hazardous exercise which tends to produce inferior performance and unexpected defects. So the time which the chip design team hoped to save by buying standard IP is lost in fixing the problems created by the porting process. 

Agile Analog IP is different: because the IP is generated fresh via the unique COMPOSA methodology, it is always optimised for the foundry, process and node in which it will be fabricated. 

‍And the chip designer has total flexibility. Do you want to change node, process or even foundry mid-design? No problem. With COMPOSA methodology, the same functional specifications and design optimisations can be applied, but with a new set of foundry design rules. And in less than four weeks from new specification to verified IP.

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With Agile Analog, IP design is in your hands. No longer constrained by the limited choice of standard IP products, chip designers can integrate more analog functions than they ever believed possible. 

When an ASIC or SoC designer evaluates standard, off-the-shelf analog IP, they are trying to discover which ready-made product best fits the specifications of their application. 

With Agile Analog, you start from a completely different place: we ask you to consider how you can optimise your design given the constraints of your foundry and process. 

Within the limits of what’s physically possible in silicon, the Agile Analog COMPOSA platform can produce the exact IP that the designer wants for their application, and that includes integrating the optimal range of functions to minimise external component count, board footprint and system cost. 

With the COMPOSA methodology, Agile Analog generates IP for a wide range of functions including signal conditioning, data conversion, security, power management, timing and sensing. 

Talk to Agile Analog and discover the scope for integrating multiple functions in one or more of these domains into your next chip design. 

For more information please contact us.