Power-On-Reset Circuit


product icon for Power-On-Reset Circuit

Product Overview

The agilePOR GP is a Power-On-Reset circuit. Based on a traditional architecture, it allows for programmable thresholds for normal and low power modes, programmable delays and includes hysteresis to avoid false resets in noisy environments.

Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. We support all the major foundries including TSMC, GlobalFoundries, Intel Foundry, Samsung Foundry, UMC and Other Foundries.

Key Information


Start-up time: max 10us • Configurable threshold • Programmable delay • Uses hysteresis to avoid false resets in noisy environments • Current consumption1: typ 100nA • Customizable design for simple SoC integration • Silicon area – Please contact Agile Analog


Hysteresis: Avoids false resets due to noisy environments • Configurable thresholds: Both upper and lower thresholds are programmable • Microprocessor held in reset during voltage rail ramp-up and during brown-out conditions

System Macros

Combine with agileVGlitch and agileLDO to create a self contained voltage attack sensor subsystem • System level Macro/Chiplet • Configured to your exact specification • Deliverables include: Verilog-a, GDSII, Liberty, PVT/Monte Carlo analysis

Block diagram for Power-On-Reset Circuit - agilePOR

Block Diagram | Power-On-Reset Circuit | agilePOR

Product Brief

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