Power Management Subsystem


Product icon for Power Management Subsystem

Product Overview

The agilePMU Subsystem is an efficient and highly integrated Power Management Unit for SoCs/ASICs. Featuring a Power-On-Reset (POR), multiple Low Drop-Out (LDO) regulators, and an associated reference generator. The agilePMU Subsystem is designed to ensure low power consumption while providing optimal power management capabilities.

Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. We support all the major foundries including TSMC, GlobalFoundries, Samsung Foundry and SMIC as well as other IC foundries and manufacturers.

Key Information


Assertion time: 5us (typ) • Configurable trigger thresholds • Programmable delay • Current consumption: 1.5uA (typ)


Output voltage: Programmable • Load current: User defined • Active current: 1uA (typ) • Power down current: 10nA (typ) • PSSR: 40dB (@DC)

agilePMU Subsystem

Start-up time: Typ 20us • Industry standard digital interface • Configurable logic to control sequencing and monitoring • Fully integrated macro •Standard AMBA APB interface

Block diagram for Power Management Subsystem - agilePMU

Block Diagram | Power Management Subsystem | agilePMU

Product Brief

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Related Information

Take a look at this selection of Agile Analog product and marketing related information. These press releases offer some interesting insights into our industry collaborations and product development work.


Agile Analog joins TSMC OIP IP Alliance Program

September 5, 2023

Digitally wrapped analog IP subsystems launched

April 25, 2023

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