agileBandGapGP General Purpose Bandgap

The agileBandGapGP consists of a bandgap reference core together with a bandgap reference voltage generator (VREF), VREF replica current generators and bias current generators. The number of output bias currents can be specified up to a maximum of 16 configurable outputs. Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable, leading to analog IP that is more verifiable, more robust and more reliable.

Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. The agileSCA TVC side-channel attack monitor core is available on CMOS and FD-SOI processes from 0.18um down to 12FF. We support all the major foundries including TSMC, GlobalFoundries, Samsung Foundry and SMIC as well as other IC foundries and Manufacturers.

Details on supported processes can be found here

Features

  • Input Voltage Range: PDK VddIO
  • Programmable Output Voltage Range
  • Untrimmed Accuracy: 5%
  • Trimmed Accuracy (single point trim): 0.5%
  • Bias Current Output: 1uA to 100uA
  • PSRR @DC : 50dB typical @DC : 50dB typical
  • @DC : 50dB typical
  • @1MHz : 40dB typical
  • Quiescent current (Iq): 50uA typical
  • Customisable design for simple SoC integration
  • Integrated Test Bus
  • Silicon Area – Process and feature dependent, please contact Agile Analog for an estimation

Benefits

Low Iq

  • Low current consumption for power sensitive applications

Multiple Outputs

  • Use as a single reference source for your SoC/ASIC

System Macro Example

The bandgap is an essential analog IP for all system designs.

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