agileCMP GP – Programmable-Threshold Comparator

The agileCMP GP programmable-threshold comparator features a user-selectable (enable/disable) hysteresis as well as programmable threshold with 10mV step size, a latched output as well as an active (unlatched) output. With a focus on long battery life, the agileCMP GP can be used to monitor external analog signals and enable wake-up events as is essential in many modern SoCs. The agileCMP GP programmable-threshold comparator is ideally suited for interrupt generation in applications such as in IoT, Security, Automotive, AI and general SoCs and ASICs.

Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. The agileCMP GP programmable-threshold comparator is available on CMOS, FD-SOI and FinFet processes from 180nm down to 12nm.

Details on supported processes can be found here


  • Configurable to your specification
  • Rail-to-rail input voltage range
  • Low threshold offset voltage
  • Programmable threshold voltage
  • Programmable hysteresis
  • Dynamic and static (latched) outputs
  • Low propagation delay


  • DFT – Incorporates analog test bus to facilitate ATE test, debug and production trim.
  • Flexible reference options -  Use the internal mux to allow either the integrated reference generator or externally supplied reference to be used.
  • Self-Contained - The IP has an integrated bias generator
  • Configuration during operation: The comparator voltage threshold can be modified using a 4bit bus during operation.
  • Low Power - Can be used to monitor external analog signals and enable wakeup/interrupt generation.
  • Optional Hysteresis - to reduce false triggers when used in a noisy environments

System Macro Example