agileLDO – Low Drop-Out Linear Regulator
The agileLDO is a linear low-dropout voltage regulator (LDO) providing precision and programmable voltage regulation across a wide range of input and output voltages. The regulator architecture provides a high dynamic performance making it suitable for demanding digital applications. Whilst the low noise and high PSSR lends itself to powering noise-sensitive analog circuits.
Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. We support all the major foundries including TSMC, GlobalFoundries, Samsung Foundry and SMIC as well as other IC foundries and Manufacturers. Please contact Agile Analog for further information.
Block Diagram:
Features:
- Input Voltage Range: PDK VddIO
- Programmable Output Voltage Range
- Current Load: <1mA to 100mA
- PSRR
- @DC Typ: 40dB
- @1MHz Typ: 20dB
- Load Regulation: Typ 0.3 %/V
- Line Regulation: Typ 50mV/A
- Quiescent current (Iq): Typ 100uA
- Customisable design for simple SoC integration
- Integrated Test Mode
- Silicon Area – Please contact Agile Analog
Benefits:
- High Performance
- Low Noise and High PSSR for noise-sensitive analog circuits
- Sense Input
- Low Noise and High PSSR for noise-sensitive analog circuits
System Macro:
- Combine with agileVGlitch and agilePOR to create a self contained voltage attack sensor sub-system
- System level Macro/Chiplet
- Configured to your exact specification
- Deliverables include: Verilog-a, GDSII, Liberty, PVT/Monte Carlo analysis
