agilePOR – Power-On-Reset
The agilePOR GP is a power-on-reset circuit. Based on a traditional architecture, it allows for programmable thresholds for normal and low power modes, programmable delays and includes hysteresis to avoid false resets in noisy environments.
Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. We support all the major foundries including TSMC, GlobalFoundries, Samsung Foundry and SMIC as well as other IC foundries and Manufacturers. Please contact Agile Analog for further information.
Block Diagram:
Key Features:
- Start-up Time: max 10us
- Configurable Threshold
- Programmable Delay
- Uses Hysteresis to avoid false resets in noisy environments
- Current Consumption1: typ 100nA
- Customisable design for simple SoC integration
- Silicon Area – Please contact Agile Analog
Benefits:
- Hysteresis
- Avoids false resets due to noisy environments
- Configurable thresholds
- Both upper and lower thresholds are programmable
- Microprocessor held in reset during voltage rail ramp-up and during brown-out conditions
System Macro:
- Combine with agileVGlitch and agileLDO to create a self contained voltage attack sensor sub-system
-System level Macro/Chiplet
-Configured to your exact specification
-Deliverables include: Verilog-a, GDSII, Liberty, PVT/Monte Carlo analysis
