- Configurable to your specification
- Up to 10 MHz output frequency
- Multiple outputs including divided clocks
- Accuracy (untrimmed) +/-30%
- Accuracy (trimmed) +/-10%
- Glitch-free operation
- Low power consumption
The agileOSC GP free-running clock is based on an RC/Ring oscillator. The clock is guaranteed to be glitch-free, including on power-up and on oscillator start-up. Furthermore, the output clock frequency will not exceed the final output frequency during start-up. The free-running clock also includes trimming options for improved accuracy as well as a range of divided output signals.
On modern SoCs, a glitch-free clock is critical for detection of security attacks and optimization of power, performance and area.
The agileOSC GP free-running clock is ideally suited for clocking and timing in applications such as in IoT, Security, Automotive, AI and general SoCs and ASICs.
Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. The agileOSC GP free-running clock is available on CMOS and FD-SOI processes from 0.18um down to 22nm.
Our engineers have extensive experience in taking complex SoCs from design to mass production. We believe that success is not just measured by delivery of CDL and GDSII, rather it extends to mass production and beyond. This is reflected in the industry-leading quality of our deliverables. Our IP comes with a complete set of deliverables for ease of integration allowing our customers to produce their SoCs reliably, quickly and effortlessly.
- Design Report
- Integration model
- Functional model
- Timing model (.LIB)
- Layout Floorplanning (LEF)
- Netlist (CDL)
- Layout (GDSII)
- Physical Verification Report
- Tapeout Checklist
- Integration Guide
- Test Guide