- Configurable design for simple SoC integration
- Targeted load current capability for minimal area
- Low-power mode for increased system efficiency
- Programmable output voltage
- Sense input for local regulation of sensitive blocks
- High PSRR
- Low Noise
The agileLDO GPA is a linear low-dropout voltage regulator (LDO) providing precision and programmable voltage regulation across a wide range of input and output voltages. The regulator architecture provides high supply rejection (PSRR) and low noise making it suitable for analog and RF applications.
The agileLDO GPA is suited for analog circuitry in applications such as IoT, Wireless, Security, Automotive, AI, Medical and general SoCs and ASICs.
Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. The agileLDO GPD low drop-out regulator is available on CMOS and FD-SOI processes from 0.18um down to 22nm. We support all the major foundries including TSMC, GlobalFoundries, Samsung Foundry and SMIC as well as other IC foundries and Manufacturers.
Our engineers have extensive experience in taking complex SoCs from design to mass production. We believe that success is not just measured by delivery of CDL and GDSII, rather it extends to mass production and beyond. This is reflected in the industry-leading quality of our deliverables. Our IP comes with a complete set of deliverables for ease of integration allowing our customers to produce their SoCs reliably, quickly and effortlessly.
- Design Report
- Integration model
- Functional model
- Timing model (.LIB)
- Layout Floorplanning (LEF)
- Netlist (CDL)
- Layout (GDSII)
- Physical Verification Report
- Tapeout Checklist
- Integration Guide
- Test Guide