Standard analog IP products from conventional IP suppliers are ready-made. That should be good, because – in theory – they are ready to be dropped into your IC design. Except that’s not how it works in practice. Because it’s off-the-shelf IP, it’s not quite right for any application. That means the chip designer has to build in work-arounds to compensate for the features of the IP that do not fit their application. The IP supplier might offer to modify its standard IP product, but modification often introduces bugs and defects which slow the customer’s path to tape-out.
The solution is Agile Analog. You specify the IP you want, to include all the features you need and taking account of all your design constraints. We then generate the IP you have specified: fully tested, fully documented, bug-free and fab-ready.
Agile Analog IP is not a standard product with a pre-determined set of features and specifications. Using our proprietary Composa™ methodology we can generate original IP for every new application. That then enables us to optimise the IP to meet the unique requirements of your application. It’s what analog designers have been crying out for. We give you the choice over what to optimise for accuracy, power consumption, die area, sensitivity, speed, or any other parameter – it’s up to you.
As analog engineers, we know that every analog circuit is different, with its own unique set of constraints and sensitivities. Now with Agile Analog, you can buy IP which reflects the unique characteristics of your design.
This is a clear way in which Agile Analog IP contrasts with conventional, off-the-shelf analog IP. Standard IP products are typically targeted at a single foundry or process. To deploy that IP to another process, it must be ‘ported’ – a risky exercise which tends to produce inferior performance and unexpected defects. So the time which the chip design team hoped to save by buying standard IP is lost in fixing the problems created by the porting process.
Agile Analog IP is different. Because the IP is generated fresh it is always optimised for the foundry, process and node in which it will be fabricated. And the chip designer has total flexibility. Do you want to change node, process or even foundry mid-design? No problem. With Agile Analog the same functional specifications and design optimisations can be applied, but with a new set of foundry design rules. And in less than four weeks from new specification to verified IP.
When an ASIC or SoC designer evaluates standard, off-the-shelf analog IP, they are trying to discover which ready-made product best fits the specifications of their application.
With Agile Analog, you start from a completely different place: we ask you to consider how you can optimise your design given the constraints of your foundry and process. Within the limits of what’s physically possible in silicon, our pioneering platform can produce the exact IP that the designer wants for their application. That includes integrating the optimal range of functions to minimise external component count, board footprint and system cost.
Agile Analog generates IP for a wide range of functions including always-on domains, data conversion, power management, security, sensing and subsystems.
Talk to the Agile Analog team and discover the scope for integrating multiple functions in one or more of these domains into your next chip design.
