agileADC 12
The agileADC 12 Analog-to-Digital Converter is a traditional Charge-Redistribution SAR ADC that is referenced to VDD, VSS. The architecture can achieve up to 12-bit resolution at sample rates up to 64 MSPS. It includes a 16-channel input multiplexor that can be configured to be buffered or unbuffered, and support differential or single-ended inputs.
Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. We support all the major foundries including TSMC, GlobalFoundries, Samsung Foundry and SMIC as well as other IC foundries and manufacturers.
Resolution: 12 bits • Sampling rate (Fs) 1: Up to 64 MSPS • Input signal bandwidth: Fs/2 • SINAD1: Typ 69 dB • ENOB1: Typ 11.3 bits • SFDR1: Typ 90 dBc • INL: +/2 LSB • DNL: +/-1 LSB • Monotonic and no missing codes • Up to 16 input channels • Integrated reference generator • Integrated calibration mode • Silicon area – Please contact Agile Analog
Digitally wrapped: AMBA-APB Interface to simplify integration, testing and operation • Provided with System Verilog models • DFT/DFM: Incorporated trim and calibration to facilitate process and/or manufacturing offsets to be adjusted • Built-in test mode • Configurable inputs: Up to 16 input channels Buffer or unbuffered • Differential or single-ended
Block Diagram | 12-bit Analog-to-Digital Converter | agileADC 12
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