agileDSCL – Digital Standard Cell Library

The agileDSCL is a compact digital standard cell library customisable for specific foundries and processes, and optimised for low-power, ultra-low-leakage, high-density or high-speed applications. It provides a selection of standard cells with functionalities essential to implement digital designs, with additional power management library to support the implementation of low-power designs. Please contact Agile Analog to discuss specialised libraries.

Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable.

Our methodology also allows us to quickly re-target our IP to different process options. We support all the major foundries including TSMC, GlobalFoundries, Samsung Foundry and SMIC as well as other IC foundries and Manufacturers.  Please contact Agile Analog for further information.

Details on supported processes can be found here


  • Compact standard cell library targeting a wide range of foundries and processes
  • Customised for low-power, ultra-low-leakage, high density or high-speed applications with choices of:
    Multiple VT and channel length
    Thick-Oxide based cells
    Various track heights
  • Power Management library for low-power designs
  • Timing models for customisable range of PVT
    High Quality library with class leading validation and models compatible with industry standard tools


Optimised for PPA targets / DFM

  • DFM-optimised


  • Agile Analog’s COMPOSATM tool enables efficient creation of libraries for specific foundries, processes, and cell architectures.

Possibility to generate models at customised PVT corners

System Macro Example