agileSMU – Sleep Management Subsystem
The agileSMU Subsystem is a low power integrated macro consisting of the essential IP blocks required to securely manage waking up a SoC from sleep mode. Typically containing a programmable oscillator for low frequency SoC operation including a RTC, a number of low power comparators which can be used to initiate the wake-up sequence, and a power-on-reset which provides a robust, start-up reset to the SoC.
Equipped with an integrated digital controller, the agileSMU Subsystem offers precise control over wake-up commands and sequencing. Status monitors provide real-time feedback on the current state of the subsystem, ensuring optimal system performance over the full product lifecycle.
Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. We support all the major foundries including TSMC, GlobalFoundries, Samsung Foundry, Intel, and SMIC as well as other IC foundries and manufacturers. Please contact Agile Analog for further information.
Block Diagram:
Features:
agilePOR - Power-On-Reset
- Start-up time: 10us
- Assertion time: 5us (typ)
- Configurable trigger thresholds
- Programmable delay
- Current consumption: 1.5uA (typ)
agileOSC_PROG - Programmable relaxation oscillator
- Programmable relaxation oscillator
- Frequency range: 32kHz to 20MHz
- Trimmed accuracy: ±2%
agileCMP LP - Low Power Comparator
- Active current: 1.5μA
- Programmable detection threshold
- Optional hysteresis
agileSMU Subsystem
- Industry standard digital interface
- Configurable logic to control sequencing and monitoring
- Fully integrated macro
- Standard AMBA APB interface
