Description of deliverables

Agile Analog provides a set of deliverables at both Initial Delivery Package (IDP) and Final Delivery Package (FDP) stages. For tapeout, all the deliveries used must come from the Final Delivery Package, however most design can be accomplished using the IDP.  This section describes the deliverables present in the delivery package.

Note: Verilog model delivered supports both Verilog and SystemVerilog.






Complete datasheet, including extracted sim results (FDP only) for key parameters across process, voltage temperature

Integration model

Verilog model for SOC integration and wiring validation

Functional model

Verilog-A functional model to understand performance


Initial & Final pin positions and area

Tapeout checklist

Tapeout checklist outlining key parameters to check pre-tapeout

Timing model

Liberty timing model for digital interfaces

Design report

This directory contains the HTML-format design reports for the IP

Integration guide

Full details for top-level integration, test requirements, and post-silicon characterisation requirements


Full layout


Complete netlist

Verification report

LVS and DRC logs including tool version numbers

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