Agile Analog provides a set of deliverables at both Initial Delivery Package (IDP) and Final Delivery Package (FDP) stages. For tapeout, all the deliveries used must come from the Final Delivery Package, however most design can be accomplished using the IDP. This section describes the deliverables present in the delivery package.
Note: Verilog model delivered supports both Verilog and SystemVerilog.
Complete datasheet, including extracted sim results (FDP only) for key parameters across process, voltage temperature
Verilog model for SOC integration and wiring validation
Verilog-A functional model to understand performance
Initial & Final pin positions and area
Tapeout checklist outlining key parameters to check pre-tapeout
Liberty timing model for digital interfaces
This directory contains the HTML-format design reports for the IP
Full details for top-level integration, test requirements, and post-silicon characterisation requirements
LVS and DRC logs including tool version numbers
Includes pinout information, usage guide and parametric details of the IP. For the FDP version, extracted simulations are used to complete the parametric tables.
Test & Integration Guide
This provides more detailed guidance on the integration process.
Outlining key parameters to check pre-tapeout.
Verilog A Model
This is a pin-exact Verilog A model, intended to be used for analog system validation in the case that the component is used as part of an analog pipeline.
This is a pin-exact Verilog file, intended for floorplanning and high level digital integration. This is a black-box only, and has no internal functionality.
Verilog Integration Model
This is a pin-exact Verilog file, intended for simulation and verification of the integration process.
This is a pin-exact LEF model, intended for floorplanning purposes. This provides an estimate of the area of the design, and can be used for top level floorplanning of the design. We aim for this to be a realistic estimate and we will always strive to deliver a final layout that fits within the LEF file boundary.
These files provide a complete timing model for the design. These are provided per-corner, and should be loaded combined with the Verilog stub for the design when read into the Place and Route tool. Depending on the block, these are either generated through Innovus as black-box timing models, or generated using Liberate. These files are expected to change between IDP and FDP as the design is finalised.
CDL [FDP delivery only]
This file includes the complete transistor-level netlist for the IP, uniquified such that any standard-cells or other common blocks will not clash names at the SoC level. This file should be used to confirm LVS results at block level, and to perform LVS at SoC level.
GDS [FDP delivery only]
This file includes the complete layout for the IP. The layer-map should be verified on import, to ensure that all layers present are imported into the SoC database. The GDS has been uniquified, such that any standard-cells or other common blocks will not clash names at the SoC level. This file should be used to confirm LVS and DRC results at block level.
Physical verification reports [FDP delivery only]
This directory includes the DRC, LVS, ERC checks performed by Agile Analog on the final CDL and GDS prior to release. Any waivers will refer to these reports, and the customer should be able to recreate these reports. Any differences should immediately be flagged.
Design Report [FDP delivery only]
This directory contains the HTML-format design reports (complete corner analysis and monte-carlo results) for the IP. The design reports should be reviewed using an HTML browser, and by opening the file index.html in each sub-directory. The results can then be scrolled through using the provided interface.