Comprehensive support to simulate, test, validate and integrate our IP.
At Agile Analog, we deliver in two phases which allows us to adapt to any changes in your requirements that may occur during the development process. These deliverables are part of the contract between Agile Analog and our customers, along with the precise delivery timeframes.
The first deliverable that we provide to customers is the IDP - Initial Delivery Package. This includes the very detailed datasheet and design report, Verilog and Verilog-A models to allow you to simulate the IP, the initial .LEF, as well as a test and integration guide. At the IDP review, we discuss and incorporate any changes necessary to the performance, power or area (PPA) of the IP to ensure you get exactly the IP you need.
We then start the layout phase and deliver the FDP – Final Delivery Package. This is a superset of the IDP, with the extracted simulation results, updated datasheet, and files needed for your tapeout: GDS, CDL and final .LEF. Even after we have delivered the FDP, if anything changes in your design, we can still quickly modify our IP to help you adapt to these changes.
Agile Analog provides a set of deliverables at both the Initial Delivery Package (IDP) and Final Delivery Package (FDP) stages. For tapeout, all the deliveries used must come from the Final Delivery Package, however most design can be accomplished using the IDP. This section describes the deliverables present in the delivery package.
Component
Description
IDP
FDP
Datasheet
Complete datasheet, including extracted sim results (FDP only) for key parameters across process, voltage temperature
Integration model
Verilog model for SoC integration and wiring validation
Functional model
Verilog-A functional model to understand performance
Functional model
Initial & final pin positions and area
Tapeout checklist
Tapeout checklist outlining key parameters to check pre-tapeout
Timing mode
Liberty timing model for digital interfaces
Design report
This directory contains the HTML-format design reports for the IP
Integration guide
Full details for top-level integration, test requirements, and post-silicon characterization requirements
Verification report
LVS and DRC logs including tool version numbers
